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www.irf.com 02-apr-10 ? 2010 international rectifier 1 27 january 2011 irs2334spbf/IRS2334MPBF 3 phase gate driver hvic features ? floating channel designed for bootstrap operation ? fully operational to 600 v ? tolerant to negative transient voltage, dv/dt immune ? gate drive supply range from 10 v to 20 v ? integrated dead time protection ? shoot-through (cross-conduc tion) prevention logic ? under-voltage lockout for both channels ? independent 3 half-bridge drivers ? 3.3 v input logic compatible ? advanced input filter ? matched propagation delay for both channels ? lower di/dt gate driver for better noise immunity ? outputs in phase with inputs ? rohs compliant typical applications ? motor control ? low power fans ? general purpose inverters ? micro/mini inverter drivers product summary topology 3 phase v offset 600 v v out 10 v ? 20 v i o+ & i o- (typical) 200 ma & 350 ma t on & t off (typical) 530 ns package options 20 leads wide body soic 28 leads mlpq 5x5 (32 leads without 4) typical connection diagram hin 1 , 2 ,3 lin 1 , 2 ,3 ho 1 , 2 ,3 lo 1 , 2 , 3 up to 600v vcc lin 1 , 2 ,3 hin 1 , 2 ,3 to load v b 1 , 2 ,3 v s 1 , 2, 3 vcc gnd com irs2334
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 2 table of contents page description 3 simplified block diagram 3 typical application diagram 4 qualification information 5 absolute maximum ratings 6 recommended operating conditions 6 static electrical characteristics 7 dynamic electrical characteristics 7 functional block diagram 8 input/output pin equivalent circuit diagram 9 lead definitions 10 lead assignments 11 application information and additional details 12 parameter temperature trends 21 package details 25 tape and reel details 27 part marking information 29 ordering information 30
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 3 description the irs2334 is a high voltage, high speed power mosfet and igbt driver with three independent high side and low side referenced output channels for 3-phase applic ations. proprietary hvic and latch immune cmos technology enables ruggedized monolithic construction. logic inputs are compatible with cmos or lsttl outputs, down to 3.3 v. the output drivers feature a high pulse curr ent buffer stage designed for minimum driver cross-conduction. propagation delays are matched to simplify use in high frequency applications. the floating channel can be used to drive n-channel power mo sfets or igbts in the high side configuration up to 600 v. simplified block diagram to high side power switches (x3) hv level shifters delay hv floating well to low side power switches (x3) schmitt trigger, minimum dead time and shoot-through protection
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 4 typical application diagram
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 5 qualification information ? industrial ?? qualification level comments: this ic has passed jedec industrial qualification. ir consumer qua lification level is granted by extension of the higher industrial level. moisture sensitivity level msl2 , 260 ? c (per ipc/jedec j-std-020) human body model class 1c (per jedec standard jesd22-a114) esd machine model class b (per eia/jedec standard eia/jesd22-a115) ic latch-up test class i, level a (per jesd78) rohs compliant yes ? qualification standards can be found at international rectifier?s web site http://www.irf.com/ ?? higher qualification ratings may be available should the user have such requirements. please contact your international rectifier sales repr esentative for further information.
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 6 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com unl ess otherwise specified. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. symbol definition min. max. units v b high side floating supply voltage -0.3 625 v s high side floating supply offset voltage v b1,2,3 - 25 ? v b1,2,3 + 0.3 v ho1,2,3 high side floating output voltage v s1,2,3 - 0.3 v b1,2,3 + 0.3 v cc low side and logic fixed supply voltage -0.3 25 ? v lo1,2,3 low side output voltage -0.3 v cc + 0.3 v in logic and analog input voltages -0.3 v cc + 0.3 v pw hin high-side input pulse width 500 ? ns dv s /dt allowable offset supply voltage slew rate ? 50 v/ns 20 lead soic ? 1.14 p d package power dissipation @ ta 25c 28 lead mlpq ? 3.363 w 20 lead soic ? 65.8 rth ja thermal resistance, junction to ambient 28 lead mlpq ? 22.3 c/w t j junction temperature ? 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 c ? all supplies are fully tested at 25 v. an internal 25 v clamp exists for each supply. recommended operating conditions for proper operation, the device should be used within the recommended conditions. all voltage parameters are absolute voltages referenced to com unless otherwise specified. the v s1,2,3 offset ratings are tested with all supplies biased at 15 v. symbol definition min. max. units v b1,2,3 high side floating supply voltage v s1,2,3 +10 v s1,2,3 + 20 v s1,2,3 static high side floating supply offset voltage ? -8 600 v s1,2,3 (t) transient high side floating supply offset voltage ?? -50 600 v ho1,2,3 high side floating output voltage v s1,2,3 v b1,2,3 v cc low side and logic fixed supply voltage 10 20 v lo1,2,3 low side output voltage 0 v cc v in logic input voltage 0 v cc v t a ambient temperature -40 125 c ? logic operation for v s of ?8 v to 600 v. logic state held for v s of ?8 v to ?v bs . ?? operational for transient negative v s of -50 v with a 50 ns pulse width. guar anteed by design. refer to the application information section of this datasheet for more details.
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 7 static electrical characteristics (v cc -com) = (v b1,2,3 -v s1,2,3 ) = 15 v and t a = 25 o c unless otherwise specified. the v in and i in parameters are referenced to com. the v o and i o parameters are referenced to com and v s1,2,3 and are applicable to the output leads lo1,2,3 and ho1,2,3 respectively. the v ccuv and v bsuv parameters are referenced to com and v s respectively. symbol definition min. typ. max. units test conditions v ih logic ?1? input voltage 2.5 ? ? v il logic ?0? input voltage ? ? 0.8 v in , th+ input positive going threshold ? 1.9 ? v in , th- input negative going threshold ? 1 ? v oh high level output voltage ? 0.9 1.4 v ol low level output voltage ? 0.4 0.6 i o = 20 ma v ccuv+ v bsuv+ v cc and v bs supply under-voltage positive going threshold 10.4 11.1 11.6 v ccuv- v bsuv- v cc and v bs supply under-voltage negative going threshold 10.2 10.9 11.4 v ccuvh v bsuvh v cc and v bs supply under-voltage hysteresis 0.1 0.2 ? v i lk offset supply leakage current ? 1 50 v b =v s = 600 v i qbs quiescent v bs supply current ? 40 120 a i qcc quiescent v cc supply current ? 300 700 a v in = 0 v i in+ logic ?1? input bias current ? 150 250 v in = 5 v i in- logic ?0? input bias current ? 1 a v in = 0 v i o+ output high short circuit pulsed current 120 200 ? i o- output low short circuit pulsed current 250 350 ? ma v o = 0 v or 15 v pw 10 s dynamic electrical characteristics v cc = v b1,2,3 = 15 v, v s1,2,3 = com, t a = 25 o c and c l = 1000 pf unless otherwise specified. symbol definition min. typ. max. units test conditions t on turn-on propagation delay 400 530 750 t off turn-off propagation delay 400 530 750 t r turn-on rise time ? 125 190 t f turn-off fall time ? 50 75 t filin input filter time 200 350 510 v in = 0v and 5v dt dead time 190 290 420 mdt dead time matching ? ? 60 mt t on , t off propagation delay matching time ? ? 50 v in = 0v & 5v external dead time 0s pm pw pulse width distortion ? ? ? 75 ns pw input =10s ? pm is defined as pw in - pw out .
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 8 functional block diagram hin1 reset set deadtime & shoot-through prevention deadtime & shoot-through prevention deadtime & shoot-through prevention uv detect input noise filter input noise filter input noise filter input noise filter input noise filter input noise filter hin2 hin3 lin2 lin1 lin3 vb1 vs1 ho2 vb2 ho1 vs2 vb3 ho3 vs3 vcc lo1 lo2 lo3 com hv level shifter delay delay delay latch uv detect latch uv detect latch uv detect reset set reset set driver driver driver driver driver driver hv level shifter hv level shifter sd sd sd
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 9 input/output pin equivalent circuit diagrams
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 10 lead definitions symbol description vcc low side and logic power supply vb1 high side floating power supply (phase 1) vb2 high side floating power supply (phase 2) vb3 high side floating power supply (phase 3) vs1 high side floating supply return (phase 1) vs2 high side floating supply return (phase 2) vs3 high side floating supply return (phase 3) hin1 logic input for high side gate driver out put ho1, input is in-phase with output hin2 logic input for high side gate driver out put ho2, input is in-phase with output hin3 logic input for high side gate driver out put ho3, input is in-phase with output lin1 logic input for low side gate driver out put lo1, input is in-phase with output lin2 logic input for low side gate driver out put lo2, input is in-phase with output lin3 logic input for low side gate driver out put lo3, input is in-phase with output ho1 high side gate driver output (phase 1) ho2 high side gate driver output (phase 2) ho3 high side gate driver output (phase 3) lo1 low side gate driver output (phase 1) lo2 low side gate driver output (phase 2) lo3 low side gate driver output (phase 3) com low side supply return
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 11 lead assignments 20 leads wide body soic 32 leads mlpq 5x5 without 4 leads 1 vs1 2 ho1 3 vb1 9 lin1 32 vb2 24 6 hin1 7 hin2 8 hin3 23 22 21 20 vcc 19 lo1 18 lo2 17 lo3 10 lin2 31 ho2 11 lin3 30 vs2 12 13 14 27 vb3 15 com 26 ho3 16 25 hs3
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 12 application information and additional details ? igbt/mosfet gate drive ? switching and timing relationships ? deadtime ? matched propagation delays ? input logic compatibility ? shoot-through protection ? under-voltage lockout protection ? truth table: under-voltage lockout ? advanced input filter ? short-pulse and noise rejection ? tolerant to negative v s transients ? pcb layout tips ? additional documentation igbt/mosfet gate drive the irs2334 hvic is designed to drive high side and low side mosfet or igbt power devices. figures 1 and 2 show the definition of some of the relevant parameters associated with t he gate driver output functionality. the output current that drives t he gate of the external power switches is defined as i o . the output voltage that drives the gate of the external power switches is defined as v ho for the high side and v lo for the low side; this parameter is sometimes generically called v out and in this case the high side and low side output voltages are not differentiated. figure 1: hvic sourcing current figure 2: hvic sinking current v s ( or ) h ( or lo ) v b ( or v cc ) i o + v h ( or v l ) + - v s ( or ) h ( or lo ) v b ( or v cc ) i o -
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 13 switching and timing relationships the relationship between the input and out put signals of the irs2334 hvic is s hown in figure 3. the definitions of some of the relevant parameter s associated with the gate driver i nput to output transmission are given. figure 3: switching time waveforms during interval a of figure 4 the hvic receives the command to turn on both the high and low side switches at the same time; correspondingly, the shoot-through prot ection prevents the high and low side signals ho and lo turn on by keeping them low. figure 4: input/output timing diagram deadtime the irs2334 hvic provides an integrat ed deadtime protection circuitry. the deadt ime interval for this hvic is fixed; while other ics within ir?s hvic portfolio feat ure programmable deadtime for greater design flexibility. the deadtime feature inserts a time interval in which both the gate driver outputs lo and ho are held off; to ensure that the power switch being turned off has fully turned off before the second power switch is turned on. this minimum deadtime is automatically inserted whenev er the external deadtime commanded by the host microcontroller is shorter than dt, while external deadtimes larger than dt are not modified by the gate driver. figure 7 illustrates the deadtime interval definition and the relationship between the output gate signals. lin or hin 50 % 50 % pw in pw out 10 % 10 % 90 % 90 % t off t on t r t f lo or ho
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 14 the deadtime interval introduced is matched with respect to the commutation from hin turning off to lin turning on, and viceversa. figure 5 defines the two deadt ime parameters dt1 and dt2. the deadtime matching parameter mdt is defined as the ma ximum difference between dt1 and dt2. figure 5: deadtime definition matched propagation delays the irs2334 hvic is designed for propagation delay matching. with this feature, t he input to output propagation delays t on , t off are the same for the low side and the high side channels; the maximum difference being specified by the delay matching parameter mt as defined in figure 6. figure 6: delay matching waveform definition input logic compatibility the irs2334 hvic is designed with inputs compatible with standard cmos and ttl outputs with 3.3 v and 5 v logic level signals. figure 7 shows how an input signal is logically interpreted. hin lin 50% 50 % 50 % 50 % dt2 dt1 ho lo
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 15 figure 7: hin & lin input thresholds shoot-through protection the irs2334 is equipped with a shoot-through protection circ uitry which prevents cross-conduction of the power switches. table 1 shows the input to output relationship in the form of a truth table. note that the hvic has non- inverting inputs (the output is in- phase with the respective input). hin lin ho lo 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 table 1: input/output truth table under-voltage lockout protection the irs2334 hvic provides under-volt age lockout protection on both the v cc low side and logic fixed power supply and the vbs high side floating power supply. figure 8 illustrates this concept by considering the v cc (or v bs ) plotted over time: as the waveform crosses the uv lo threshold, the under-volt age protection is entered or exited. upon power up, should the v cc voltage fail to reach the v ccuv+ threshold, the gate driver outputs lo and ho will remain disabled. additionally, if the v cc voltage decreases below the v ccuv- threshold during normal operation, the under-voltage lockout circuitry will s hutdown the gate driver outputs lo and ho. upon power up, should the v bs voltage fail to reach the v bsuv threshold, the gate driver output ho will remain disabled. additionally, if the v bs voltage decreases below the v bsuv threshold during normal operation, the under- voltage lockout circuitry will shutdown the high side gate driver output ho. the uvlo protection ensures that t he hvic drives external power dev ices only with a gate supply voltage sufficient to fully enhance them. without this protection, t he gates of the external pow er switches could be driven
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 16 with a low voltage, which would result in power swit ches conducting current while with a high channel impedance, which would produce very high conduction losse s possibly leading to power device failure. figure 8: uvlo protection truth table: under-voltage lockout table 2 provides the truth table for the irs2334 hvic. the 1 st line shows that for v cc below the uvlo threshold both the gate driver outputs lo and ho are disabled. a fter v cc returns above v ccuv , the gate driver outputs return functional. the 2 nd line shows that for v bs below the uvlo threshold, the gate dr iver output ho is disabled. after v bs returns above v bsuv , ho remains low until a new rising transition of hin is received. the last line shows the normal operation of the hvic. outputs vcc vbs lo ho uvlo v cc < v ccuv 0 0 uvlo v bs 15 v < v bsuv lin 0 normal operation 15 v 15 v lin hin table 2: uvlo truth table advanced input filter the irs2334 hvic provides an advanced i nput filter that improv es the input/output pulse symmetry of the signals processed by the hvic. this input filt er is inserted at the hin and lin input pins. the working principle of the filter is shown in figures 9 and 10. figure 9 shows a typical input filter and the asymmetry it produces on its output signal. the upper waveforms of example 1 show an input signal with a pulse dur ation mush longer than the filtering time t filin ; the resulting output v ccu - ( or bsu - ) uvlo protection ( gate driver outputs disabled ) norma operation norma operation v ccu + ( or bsu + ) v cc ( or b ) time
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 17 signal has a duration given approximately by the difference between the input signal and t filin . the lower waveforms of example 2 show an input signal with a pul se duration slightly longer than the filtering time t filin ; the resulting output signal has a durati on given approximately by the diffe rence between the input signal and t filin, much shorter than it should be. figure 10 shows the advanced input filter and the symmetry it produc es on its output signal. the upper waveforms of example 1 show an input signal with a pulse duration much longer than the filtering time t filin ; the resulting output signal has appr oximately the same duration as the input signal. the lower waveforms of example 2 show an input signal with a pulse duration slightly longer than the filtering time t filin ; the resulting output signal has approximately the same duration as the input signal. figure 9: typical input filter fi gure 10: advanced input filter short-pulse and noise rejection the advanced input filter that improv es the input/output pulse symmetry of the signals processed by the hvic also helps the rejection of noise spikes and of short pulses on the input signals. input signals with a pulse durati on less than the filtering time t filin will be filtered out. in figure 11 example 1 shows an input signal in the low state with superim posed positive noise spikes of duration less than t filin ; the advanced input filter filters out the noise spikes and the output signal re mains in the low state. example 2 shows an input signal in the high state with superimpos ed negative noise spikes of duration less than t filin ; the advanced input filter filters out the noise spikes and the output si gnal remains in the high state. example 1 example 2 figure 11: noise rejection of the advanced input filter
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 18 the measured characteristic of the advanc ed input filter is shown in figure 12. on the left side the characteristic for narrow on pulses is shown (short positive pulse) wh ile on the left side the characteristic for narrow off pulses is shown (short negative pulse). the x- axis represents the input pulse duration pw in , while the y-axis the resulting output pulse duration pw out . for pulses with input pulse duration pw in less than the filtering time t filin the resulting output pulse duration pw out is zero because the filter rejects the input signal. for pulses with input pulse duration pw in greater than the filtering time t filin the resulting output pulse duration pw out tracks the input pulse durations well, the higher t he duration the better the symmetry. time (ns) figure 12: measured advanced input filter characteristic the difference between the output pulse duration pw out and the input pulse duration pw in of both the narrow on and narrow off cases is shown in figure 13. t he x-axis represents the input pulse duration pw in , while the y-axis the resulting difference pw out ?pw in . figure 13: difference between the input pulse duration and the output pulse duration tolerant to negative vs transients a common problem in today?s high-power switching conver ters is the transient response of the switch node?s voltage as the power devices switch on and off quickly while carrying a large current. a typical 3-phase inverter circuit is shown in figure 14; where we define the power switches and diodes of the inverter. if the high-side switch (e.g., the igbt q1 in figures 15 and 16) switches off, while the u phase current is flowing to an inductive load, a current commutation occurs from hi gh-side switch (q1) to the diode (d2) in parallel with the low-side switch of the same inverter leg. at the same instance, the voltage node v s1 , swings from the positive dc bus voltage to the negative dc bus voltage.
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 19 figure 14: three phase inverter q1 on d2 v s1 q2 off i u dc+ bus dc- bus figure 15: q1 conducting figure 16: d2 conducting also when the v phase current flows from the inductive load back to the inverter (see figures 17 and 18), and q4 igbt switches on, the current commutation occurs from d3 to q4. at the same instance, the voltage node, v s2 , swings from the positive dc bus vo ltage to the negative dc bus voltage. dc+ bus q3 off d3 d4 dc- bus v s2 q4 off i v figure 17: d3 conducting figure 18: q4 conducting however, in a real inverter circuit, the v s voltage swing does not stop at the le vel of the negative dc bus, rather it swings below the level of the negative dc bus . this undershoot voltage is called ?negative v s transient?.
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 20 the circuit shown in figure 19 depicts one leg of the th ree phase inverter; figures 20 and 21 show a simplified illustration of the commutation of the current between q1 and d2. the parasitic inductances in the power circuit from the die bonding to the pcb tracks are lumped together in l c and l e for each igbt. when the high-side switch is on, v s1 is below the dc+ voltage by the voltage drops associated with the power switch and the parasitic elements of the circuit. when the high-side power switch turns off, t he load current momentarily flows in the low-side freewheeling diode due to the inductive load connected to v s1 (the load is not shown in these figures). this current flows from the dc- bus (which is connected to the com pin of the hvic) to the load and a negative voltage between v s1 and the dc- bus is induced (i.e., the com pi n of the hvic is at a higher potential than the v s pin). figure 19: parasitic elements figure 20: v s positive figure 21: v s negative in a typical motor drive system, dv/dt is typically designed to be in the range of 3-5 v/ns. the negative v s transient voltage can exceed this range during some event s such as short circuit and over-current shutdown, when di/dt is greater than in normal operation. international rectifier?s hvics have been designed for t he robustness required in many of today?s demanding applications. an indication of the irs2334?s robustness c an be seen in figure 22, where there is represented the irs2334 safe operating area at v bs =15v based on repetitive negative v s spikes. a negative v s transient voltage falling in the grey area (outside soa) may lead to ic permanent damage; vice versa unwanted functional anomalies or permanent damage to the ic do not appear if negative vs transients fall inside soa. at v bs =15v in case of -v s transients greater than -16.5 v for a period of time greater than 50 ns; the hvic will hold by design the high-side output s in the off state for 4.5 s.
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 21 figure 22: negative v s transient soa @ vbs=15v even though the irs2334 has been shown able to handle thes e large negative vs transient conditions, it is highly recommended that the circuit des igner always limit the negative v s transients as much as possible by careful pcb layout and component use.
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 22 pcb layout tips distance between high and low voltage components: it?s strongly recommended to place the components tied to the floating voltage pins (v b and v s ) near the respective high voltage portions of the device. please see the case outline information in this datasheet for the details. ground plane: in order to minimize noise coupling, the ground plane should not be placed under or near the high voltage floating side. gate drive loops: current loops behave like antennas and are able to receive and transmit em noise (see figure 23). in order to reduce the em coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as much as possible. moreover, current can be injected inside the gate drive loop via the igbt collector-to-gate parasitic capacitance. the paras itic auto-inductance of t he gate loop contributes to developing a voltage across the gate-emi tter, thus increasing the possib ility of a self turn-on effect. figure 23: antenna loops supply capacitor: it is recommended to place a bypass capacitor between the vcc and com pins. this connection is shown in figure 24. a ceramic 1 f ceramic capacitor is suitable for most applications. this component should be placed as close as possible to t he pins in order to reduce parasitic elements. hin 1 , 2 ,3 lin 1 , 2 ,3 ho 1 , 2 ,3 lo 1 , 2 , 3 up to 600v vcc lin 1 , 2 ,3 hin 1 , 2 ,3 to load v b 1 , 2 , 3 v s 1 , 2 , 3 vcc gnd com figure 24: supply capacitor r g v ge gate drive loo c gc i gc v b ( or cc ) h ( or ) v s ( or )
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 23 routing and placement: power stage pcb parasitic elements can c ontribute to large negative voltage transients at the switch node; it is recommended to limit the phas e voltage negative transients. in order to avoid such conditions, it is recommended to 1) minimize the high-side source to low-side collector distance, and 2) minimize the low-side emitter to negative bus rail st ray inductance. however, where negative v s spikes remain excessive, further steps may be taken to reduce the spik e. this includes placing a resistor (5 ? or less) between the v s pin and the switch node (see figure 25), and in some cases using a clamping diode between com and v s (see figure 26). see dt04-4 at www.irf.com for more detailed information. figure 25: v s resistor figure 26: v s clamping diode additional documentation several technical documents related to the use of hvics are available at www.irf.com ; use the site search function and the document number to quickly locate them. below is a short list of some of these documents. dt97-3: managing transients in control ic driven power stages an-1123: bootstrap network analysis: focusi ng on the integrated bootstrap functionality dt04-4: using monolithic high voltage gate drivers an-978: hv floating mos-gate driver ics parameter temperature trends figures 27-44 provide information on the experimental performance of the irs2334 hvic. the line plotted in each figure is generated from actual ex perimental data. a small number of individual samples were tested at three temperatures (-40 oc, 25 oc, and 125 oc) in order to generate the experimental curve. the line labeled exp. consist of three data point s (one data point at each of the tested temperatures) that have been connected together to illustrate the understood temperat ure trend. the individual data points on the curve were determined by calculating the av eraged experimental value of the param eter (for a given temperature). t load v s ho v b l co r vs dc + bu dc - bu c bs t load v s ho v b l co r vs d vs dc + bu dc - bu c bs
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 24 0 100 200 300 400 500 600 700 800 -50-25 0 255075100125 temperature ( o c) t on (ns) exp. 0 200 400 600 800 1000 -50-25 0 25 50 75100125 temperature ( o c) t off (ns) exp . fig. 27. turn-on propagation delay vs. temperature fig. 28. turn-off propagation delay vs. temperature 0 100 200 300 400 -50 -25 0 25 50 75 100 125 te mpe rature ( o c) t r (ns) exp . 0 10 20 30 40 50 60 70 80 90 100 -50 -25 0 25 50 75 100 125 temperature ( o c) t f (ns) exp . fig. 29. turn-on rise time vs. temperature fig.30. turn-off fall time vs. temperature 0 1 2 3 4 -50 -25 0 25 50 75 100 125 temperature ( o c) v in _th- (v) exp . 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) v ol (mv) exp. fig. 31. input negative going threshold vs. temperature fig. 32. low level output voltage vs. temperature
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 25 0 5 10 15 20 -50 -25 0 25 50 75 100 125 temperature ( o c) lleak1_vccmax (ua) exp . 0 1 2 3 4 -50 -25 0 25 50 75 100 125 temperature ( o c) i qcc1 (ma) exp . fig. 33. offset supply leakage current vs. temperature fig. 34. quiescent vcc supply current vs. temperature 0 1 2 3 4 -50 -25 0 25 50 75 100 125 temperature ( o c) i qcc0 (ma) exp . 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 te mpe rature ( o c) i qbs10 (ua) exp . fig. 35. quiescent vcc supply current vs. temperature fig. 36. quiescent vbs supply current vs. temperature 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 te mpe rature ( o c) i qbs11 (ua) exp . 0 3 6 9 12 15 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc uv th- (v) exp . fig. 37. quiescent vbs supply current vs. temperature fig. 38. vcc s upply under-voltage negative going threshold vs. temperature
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 26 0 3 6 9 12 15 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc uv th+ (v) exp . 0 3 6 9 12 15 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs uv th- (v) exp . fig. 39. vcc supply under-voltage positive going threshold vs. temperature fig. 40. vbs supply under-voltage negative going threshold vs. temperature 0 3 6 9 12 15 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs uv th+ (v) exp . 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 te mpe rature ( o c) io+ (ma) exp . fig. 41. vbs supply under-voltage positive going threshold vs. temperature fig. 42. output high short circuit pulsed current vs. temperature 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 te mpe rature ( o c) io- (ma) exp . -20 -15 -10 -5 0 -50 -25 0 25 50 75 100 125 temperature ( o c) vs1_rs_domin (v) exp. fig. 43. output low short circuit pulsed current vs. temperature fig. 44. max ?vs vs. temperature
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 27 package details
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 28 package details 28 (32 ? 4) lead mlpq 5x5mm
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 29 tape and reel details carrier tape dimension for 20soicw cod mi ma mi ma a 11.9 12.1 0.46 0.47 b3.9 4.1 0.15 0.16 c 23.7 24.3 0.93 0.95 d 11.4 11.6 0.44 0.45 e 10.8 11.0 0.42 0.43 f 13.2 13.4 0.52 0.52 g 1.5 n/ 0.05 n/ h 1.5 1.6 0.05 0.06 reel dimensions for 20soicw cod mi ma mi ma a 329.6 330.2 12.97 13.00 b 20.9 21.4 0.82 0.84 c 12.8 13.2 0.50 0.51 d 1.9 2.4 0.76 0.09 e 98.0 102.0 3.85 4.01 f n/ 30.4 n/ 1.19 g 26.5 29.1 1.0 1.14 h 24.4 26.4 0.9 1.03 metri imperial metri imperial e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction a h f e g d b c
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 30 tape and reel details: 28 (32 ? 4) lead mlpq 5x5mm
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 31 part marking information
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 32 ordering information standard pack base part number package type form quantity complete part number tube/bulk xxx irs2334 spbf soic20w tape and reel xxx irs2334 strpbf tube/bulk xxx irs2334 mpbf irs2334 28l mlpq 5x5mm (32 leads without 4) tape and reel xxx irs2334 mtrpbf the information provided in this document is believed to be accu rate and reliable. however, international rectifier assumes no responsibility for the consequences of the use of this information. international r ectifier assumes no responsibility fo r any infringement of patents or of other rights of third parties which may result from the use of this information. no license is granted by implication or ot herwise under any patent or paten t rights of international rectifier. the specifications mentioned in this document are subj ect to change without notice. this document supersedes and r eplaces all information previously supplied. for technical support, please contact ir?s technical assistance center http://www.irf.com/technical-info/ world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105
irs2334spbf/mpbf www.irf.com ? 2010 international rectifier 33 revision history revision date change comments 5.0 24 jun 2009 ramanan updated lead assignment, mlpq 5x5 package information and absolute max ratings to reflect 25v capability 5.1 30 jun 2009 updated: format, lead assignment, functional block diagram, added: simplified block diagram, typical applic ation diagram, qualification information, application details, parameters temperat ure trend, tape and reel detail, order information, revision history removed: inputs internally clamped at 5.2v in static electric al characteristic 5.2 3 july 2009 lead definition corrected, delay matching waveform definition figure added 5.3 aug 2009 package and tape & reel details fo r mlpq 32-4 leads 5x5 added, package thermal parameters added 5.4 12 nov 2009 advanced input filter section added 5.5 tbd values in static el ectrical characteristics updated 5.6 9 dec 2009 changed mm esd rating from class c to class b 5.7 12 mar 2010 parameter limits updated: iqcc, iqbs, iin+ 5.8 02 apr 2010 i o+ , i o- values corrected 5.9 26 jan 2011 update temperature dependence tables, uvcc hyst corrected 5.10 31 jan 2011 include the IRS2334MPBF in the datasheet title

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